The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.
The design of ever-smaller FETs with short channel lengths makes it desirable to minimize the depth of the source/drain junctions to thereby provide shallow junctions. Shallow junctions are desirable to avoid lateral diffusion of implanted dopants into the channel, since such diffusion contributes to leakage of current and poor breakdown performance. Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In an SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film of silicon is formed on the buried oxide film. A more recent variation of the SOI substrate is the so-called “extremely thin” SOI (ETSOI) substrate. ETSOI substrates may be used to form fully depleted charge carrier transistor devices (i.e., having a concentration of charge carriers present in the channel on the order of 103 atoms/cm3 or less), and use an extremely-thin silicon channel (for example from about 3 nm to 20 nm in thickness), wherein the majority of carriers are fully depleted (FD) during operation.
ETSOI substrates, however, due to their thin channels, can only support FETs that operate at less than about 5 volts (V) (i.e., “low voltage” transistors). This is due to the fact that a high electric field is generated in the thin channel at higher voltages, which can cause parasitic capacitance between FETs and device performance problems. Thus, integrated circuits that require both low voltage FETs and/or medium voltage (i.e., operating from about 5 volts to about 20 volts) and/or high voltage (i.e., operating above about 20 volts) FETs have heretofore not been able to take advantage of the scaling benefits of ETSOI substrates.
Accordingly, it is desirable to provide methods for fabricating integrated circuits on ETSOI substrates that include low voltage FETs in addition to medium and/or high voltage FETs. Additionally, it is desirable to provide methods for the fabrication of such integrated circuits that are easily integrated into existing process flow schemes used in semiconductor fabrication facilities. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.